Here I will be showing my PLL designs. New designs and updates are coming soon.
1.2 GHz Fixed-Frequency Clock-Multiplying Digitally Controlled PLL - Digitally controlled PLL with digital Phase-Frequency Detector, Digital Divider, Digital Output Buffer, Analog Passive Loop Filter, Charge Pump and current-starved VCO composed of inverters. The Input frequency is 200 MHz the fixed output frequency is 1.2 GHz. Implemnted on a IBM 180nm 7RF process.